The present disclosure relates in general to data processing systems and, in particular, to techniques for requesting data associated with a cache line in symmetric multiprocessor systems.
Traditionally, symmetric multiprocessor (SMP) systems, such as server computer systems, have included multiple processing units all coupled to a system interconnect, which has included one or more address, data, and control buses. Coupled to the system interconnect was a system memory, which represented the lowest level of volatile memory in the multiprocessor computer system and which was generally accessible for read and write access by all processing units. In order to reduce access latency to instructions and data residing in the system memory, each processing unit was typically further supported by a respective multi-level cache hierarchy, the lower level(s) of which may be shared by one or more processor cores.